• Dual Band 25.78125G/28Gbps SerDes/CDR Available in TSMC28nm 9LM HPC+ Available 2Q 2018
    • Features
      • Eye Monitor accessible through I2C
      • Digital temperature readout
      • 3 TAP FIR TX VML Output Driver
      • Receiver Input CTLE
      • Low Noise APLL based on LC oscillator
      • I2C Interface
      • Built in PRBS 9 and PRBS 31
      • Adjustable Loop Bandwidth
      • Lock Detection
      • Available in 250um Pitch or Higher with DCAP Wrapper Cell
      • Low Power
      • Voltage Regulation on VCO
  • Multiple TSMC 130nm and 180nm Low Noise PLL
  • Nanopower/High Voltage  XFAB XC06 - 600nm 
  • Patented 'Numalock' Fractional Frequency Synthesis